The present invention relates generally to the on-chip inductors in integrated circuits, more particularly to the design and construction of parallel stacked symmetrical and differential on-chip inductors.
The integration of radio-frequency (RF) functions into CMOS implementations and miniaturization has led to low cost communication solutions and has given fillip to the demand for wireless/mobile communication applications including mobile/smart phones, WIFI, Bluetooth, GPS and other applications. The performance of these applications is continuously improving. These RF implementations necessarily require inductors to be integrated on the CMOS chip and, thus, on-chip inductors continue to be the subject of research and development from early stages of RFCMOS technology. Major drawback of implementing the inductors on the CMOS chip is the relatively lower quality factor (Q). The improvement in the Q factors continues to be the subject of research till date. The implementation of on-chip inductors in the differential and/or symmetrical configurations which are used in differential circuits to suppress the common mode noise and improved Q factor is frequently used in RF CMOS integrated circuit designs. The research in this area is still being actively carried out as the challenge remains to design and fabricate higher Q differential inductors suitable for radio-frequency integrated circuits (RFIC) to support the wireless/mobile communication applications.
High Q inductors are mainly required in sharp cut-off frequency circuits, low noise impedance matching circuits, low phase noise oscillators, high gain circuits, etc. The higher Q is achieved by adding a thick metal layer on the top of silicon substrate and the concentric metal spirals are defined in this metal layer to implement high Q inductance. The thick metal layer, however, adds to the cost and process complexity. The alternative and relatively lower cost solution is to make use of multi-level metal layers available in standard CMOS and implementing the inductor spirals out of the parallel connected stacks of these multiple metal levels.
The challenge of designing and fabricating high Q inductors, specifically parallel stacked symmetrical and differential inductors, is to improve the Q factor while maintaining the inductance value, self resonance frequency and other symmetrical and differential performance parameters of the inductor. In symmetrical and/or differential inductors, the spirals cross over the other spirals through bridge regions. Conductors in the bridge regions typically lie in the metal levels close to the substrate which typically have higher resistivity and thus impact Q factor.